Improved one-column sorting of omnisci RDMBS by 2.5 times https://github.com/intel-ai/omniscidb Participated in re-factoring of omnisci (deleted above 40000 GEO supporting lines) Implemented line info generating for operations inside bundles according to DWARF4 Specification in llvm compiler

Designed a Loop Representation for internally developed programming language IR Implemented scanner, syntax parsing for the converter from Lua to internally developed programming language. Designed and implemented AST for the converter from Lua to internally developed programming language, visual graph representation for it. The implementation language was golang

Found opportunities for performance improvement for benchmarks and user's applications Participated in developing internal performance analysis tools, in particular, developed utilities for extra-spills analysis Proposed the new optimization for improvement of code cache utilization and inlining algorithm

Participated in development of LLVM-based optimizing compiler for one of Samsung DSP. Supported several arithmetic and moving instructions, implemented bundling (packetizing) machine instructions, implemented recognition of loops – candidates for hardware loops and code generating for them. Participated in development of Neural Network optimizing compiler for Samsung Neural Processing Units. Participated in development of the C# compilers for mobile platforms Improved Startup Time of GUI C# Application on Tizen for about 15%. Received the thank-you-letter from the Microsoft .NET team following the results of 2017 (www.github.com/sergign60) – providing Runtime support for ARM processors. Participated in preparation of the training course for students on the subject "Compilers and System Programming" (www.github.com/sergign60/CrashCourse)

Worked on code generation optimizations for VLIW archtecture Elbrus. Worked on template (written on native Elbrus assembler) interpreter for Java VM optimizer for Elbrus. Directed works on improvement of performance of Waratek JVM (a clone of Apache Harmony project - https://harmony.apache.org) Performance was signicantly improved for 40% on SPECjvm2008 and for 25% on SPECjbb2005 and reached about 90% of openjdk6 performance. Improved peephole, register allocation, inlining, loop unrolling, static profiling, loop versioning optimizations.

04/2009-05/2013 member of Performance Compiler Tracking group Various suites were added to the used performance testing system for performance tracking of Intel compiler. Methods of automated performance testing on embedded systems – VxWorks and QNX – were developed and implemented on Perl programming language. CPU2000 tests were integrated into EEMBC 2.0 test harness for performance testing on embedded systems. Quality and performance tests for testing of Intel Larrabee compiler were developed. Server-Client model of Automated Performance Testing System (ATS) - analog of TeamCity - for heterogeneous (windows, linux, embedded systems) performance machine pool were designed, developed and implemented. Provided automated execution methods for various benchmarks including for KNF-KNC systems. Designed ATS Reporting System with using Microsoft ,NET environment and jQuery successors packages (Javascript) 06/2007-03/2009 a member of CM (C compiler for Intel GenX) group Data structures for loop representation in CMIR (CM Intermediate Representation) developed and implemented. Loop unrolling algorithm developed and implemented. Data structures and algorithms for Global Data Flow Analysis in CM compiler developed and implemented. Some optimizations such as block merging, deleting unreachable code, constant folding, dead code elimination, copy propagation, definition hoisting developed and implemented. Provided proposals on Supporting Heterogeneous (multi-platform) Debugging in CM compiler, some new features and extensions for Microsoft STI and Intel compiler DGI developed and proposed. Intel Russia/CIS Achievement Award For great contribution into Intel leadership and innovation in compiler technologies for GPUs Intel VSG Award In recognition for the development and delivery of the C for Media Compiler alpha release for GenX Processor 01/2007-06/2007 member of Static Verifier group Fixed some bugs in Static Verifier that allowed significantly improved compile time and memory usage in Static Verifier. Proposed reordering Static Verifier phases for more effective memory usage. Proposed and implemented improved method of debugging information reading. 08/2004-12/2006 member of Loop Optimization (HLO) group Fixed and investigated about 100 bugs for HLO, PAROPT and HPO components of Intel compiler. Designed and implemented IF fusion algorithm. New method of finding fusion candidates was developed and implemented that allowed significantly improved the quality of the existing fusion algorithm in HLO. Designed and implemented memset/ memcpy recognition for loop nests. Provided proposals on Improving Phase Ordering in PAROPT-HLO, Implementing Type Alias Analysis in Intel compiler and Improving Dependence Analysis in HLO

Participated in development of the Unified Back-End (UBE) for Sun compilers for Intel platform. Participated in development of Sun Fortran-90 and Fortran-77 compilers. Participated in development of various service testing tools for these compilers. Translated into Russian Steven S. Muchnick’s “Advanced Compiler Design Implementation” (with Serguei Wenitzky, not published).

Participated in designing and implementation of the Fortran 90 compiler for "Elbrus-3"​ and IBM PC. Participated in the development and implementation of the "Elbrus-2" FORTRAN 8X compilers.